Today's sophisticated SoC (System on Chip) designs are rapidly evolving and nearly doubling in size with each generation. Indeed, complex designs have nearly exceeded 50 million gates. This complexity, combined with the use of devices in industrial and mission-critical products, has made complete design verification an essential element in the semiconductor development cycle. Ultimately, this means that every chip designer, system integrator, and application software developer must focus on design verification.
Hardware emulation provides an effective way to increase verification productivity, speed up time-to-market, and deliver greater confidence in the final SoC product. Even though individual intellectual property blocks may be exhaustively verified, previously undetected problems appear when the blocks are integrated within the system. Comprehensive system-level verification, as provided by hardware emulation, tests overall system functionality, IP subsystem integrity, specification errors, block-to-block interfaces, boundary cases, and asynchronous clock domain crossings. Although design reuse, intellectual property, and high-performance tools all help by shortening SoC design time, they do not diminish the system verification bottleneck, which consumes 60-70% of the design cycle. As a result, designers can implement a number of system verification strategies in a complementary methodology including software simulation, simulation acceleration, hardware emulation, and rapid prototyping. But, for system-level verification, hardware emulation remains a favorable choice due to, superior performance, visibility, flexibility, and accuracy.
A short history of hardware emulation: software programs would read a circuit design file and simulate the electrical performance of the circuit very slowly. To speed up the process, special computers were designed to run simulators as fast as possible. IBM's Yorktown “simulator” was the earliest (1982) successful example of this—it used multiple processors running in parallel to run the simulation. Each processor was programmed to mimic a logical operation of the circuit for each cycle and may be reprogrammed in subsequent cycles to mimic a different logical operation. This hardware ‘simulator’ was faster than the current software simulators, but far slower than the end-product ICs. When FPGAs became available in the mid-80's, circuit designers conceived of networking hundreds of FPGAs together in order to map their circuit design onto the FPGAs and the entire FPGA network would mimic, or emulate, the entire circuit. In the early 90's the term “emulation” was used to distinguish reprogrammable hardware that took the form of the design under test (DUT) versus a general purpose computer (or work station) running a software simulation program.
Soon, variations appeared. Custom FPGAs were designed for hardware emulation that included on-chip memory (for DUT memory as well as for debugging), special routing for outputting internal signals, and for efficient networking between logic elements. Another variation used custom IC chips with networked single bit processors (so-called processor based emulation) that processed in parallel and usually assumed a different logic function every cycle.
Physically, a hardware emulator resembles a large server. Racks of large printed circuit boards are connected by backplanes in ways that most facilitate a particular network configuration. A workstation connects to the hardware emulator for control, input, and output.
Before the emulator can emulate a DUT, the DUT design must be compiled. That is, the DUT's logic must be converted (synthesized) into code that can program the hardware emulator's logic elements (whether they be processors or FPGAs). Also, the DUT's interconnections must be synthesized into a suitable network that can be programmed into the hardware emulator. The compilation is highly emulator specific.
To further speed up hardware emulation, some of the latest emulators separate a processor board from the hardware emulator allowing for more effective utilization of the hardware emulator. For example, FIG. 1 shows an hardware emulation environment 10 including a processor board 12, a hardware emulator 14, a PC that runs a software debugger 16 (hereinafter called a software debugger host), and an emulator host 18. The processor board 12 generally includes a processor 20 that incorporates on-chip debug facilities, together with processor supporting logic. The processor's on-chip debug facilities are coupled via cabling 22 to the software debugger host 16. Using the software debugger, a system developer can control and debug the system software by setting software breakpoints and monitoring the processor registers. The hardware emulator 14 models part or all of the functions of the DUT and includes multiple field programmable gate arrays (FPGAs) (or processor arrays) that serve as a breadboard for implementing the desired integrated circuit design. More specifically, the emulator host 18 programs the FPGAs with the integrated circuit design being tested and monitors the various hardware components in the system. For example, as shown in FIG. 1, there are generic design blocks 24, 26, such as memory and peripherals, and a system bus 28 connecting the hardware emulator 14 to the processor board 12. The processor 20 is clocked by an emulator clock 30. The hardware emulator includes a design having a memory map that is split into various parts, such as read-only instruction memory (including system BIOS and CPU run-time code), R/W data and stack sections, and memory locations for configuration of peripherals. The emulator host 18 controls and monitors the state and activity of the hardware emulator, including downloading the design and uploading state information. Thus, the hardware emulation environment is used to debug both hardware and software of the design allowing the designer to be more certain that the final SoC produced is fully functional.
However, there are problems with such an hardware emulation system. For example, current hardware emulation systems run from 100 KHz to 1.5 MHz, whereas the actual circuits in silicon run at several hundred megahertz. Of course, a problem with the slower clock speeds of the hardware emulator is that hardware emulation can take several hours, which significantly slows the overall verification process.
One possible solution to speed up the verification process is to skip sections of software that are already well proven. For example, the BIOS of an operating system is generally well established and unnecessary to test again. However, software designers do not want to bypass such sections for fear of missing a state change, which may precipitate an error in the system when in silicon not found during testing. Generally, good engineering principles suggest that the software should be tested in a mode as close as possible to the actual use.
Thus, it is desirable to speed up hardware emulation while maintaining the overall integrity of the testing process.